Verilog Tag Script 2  Go To Script Pool
VTAGS is an Perl script used to create a Vi/Vim tags file from Verilog source files. When used with Vi/Vim, a tags file lets you jump quickly between files as you peruse source code.

VTAGS searches for module, task, and function declarations in the Verilog source(s) and adds them to the tags file. Once this is done, you use the ctrl-], ctrl-t, and :ta commands to cruise through your source files.

The Perl script is rather brute force and is not a full Verilog parser - it can get confused! If you use a clean Verilog coding style, you should have no problems. The script currently only accepts file names that end in .v.  If you don't like this, feel free to change the source code.

# Copyright P&B, Inc.  1998
# http://www.probo.com/

#! /usr/local/bin/perl
#
# Create a Vi style tags file for Verilog files
# Scan Verilog files to extract function/task/module keywords
#

@ARGV[0] || die "usage:\n vtags.pl {[-f file_of_file_names] | [file]} ...\n" ;

$in_comment = 0 ;
$file_cnt = 0 ;

# expand command line to remove '-f' flags
while ($n_arg = shift) {
if ($n_arg eq "-f") {
    # process the list of files
    $n_arg = shift ;
    open(FILES, $n_arg) || die "can't open cmd line file $n_arg\n" ;
    while (<FILES>) {
    chop ;
    s/^.* // ;                 # remove any leading -flags
    /\.[vV]\s*$/ && push(@files, $_) ;    # save only .v files
    }
} elsif ($n_arg =~ /\.[vV]\s*$/ ) {
    push (@files, $n_arg) ;    # save .v files from cmd line
}
}

# print "all Verilog input files are: @files\n" ;

# read all the files scanning for module/task/function keywords
foreach $file (@files) {
open (INPUT, $file) || die "can't open verilog file $file\n" ;
$file_cnt++ ;
while (<INPUT>) {
    # Scan each line for keywords while keeping track of comments
    # This can be written much more concisely, but this tries to
    # minimize the code for each common case. Using this style
    # was about 3x faster than the original 'concise' code!
    if (!$in_comment) {
    # not currently in a block comment
    if (m,/[/*],) {
        # some kind of start of comment is in the line
        s,//.*$|/\*.*\*/,, ;    # strip //.... and /*....*/ comments
        $in_comment = s,/\*.*$,, ;    # remove /*...$ comment text
    }

    # check for keywords, remember them in the tags array
    if (/\b(module|task|function)\s+(\w+)/) {
        $tags{$2} = "$file\t$." ;
    }
    } else {
    # we're in a /* style comment already
    if (s,^.*\*/,,) {
        # we've found the ending */ for the comment, keep checking

        # strip //.... and /*....*/ comments from the line
        s,//.*$|/\*.*\*/,, ;

        # remove the text from the start of another /* comment
        $in_comment = s,/\*.*$,, ;
        if (/\b(module|task|function)\s+(\w+)/) {
        # got another tag to add
        $tags{$2} = "$file\t$." ;
        }
    }
    }
}
close (INPUT) ;
}

# send out the tags file
open(TAGS, ">tags") || die "can't open tags file\n" ;
foreach $i (sort keys (%tags) ) {
print TAGS "$i\t$tags{$i}\n" ;
$tag_cnt++ ;
}
print "$file_cnt files scanned, $tag_cnt tags found\n" ;

 

Other Scripts:

Batch Simulation
Compare Files
Convert
Def2Verilog
Gen XOR Tree
GetValue
IHEX2VHEX
nand tree
Name Instance
OnesCompSum
Preprocessor
Verilog Tag

Verilog Tag2
Verilog2DEF
VHDL2HTML
VRename
XNF2VHDL

 

Products:

Undertow Suite
Undertow
Interactive_tool
Optimizing_tool
VeriPower
Power_tool
Toggle_tool
Express_VCT
Personal_VCT
VBIT«
verilog2vhdl™
vhdl2verilogmkt
Script Pool


 

 Company    Products     News    Assistance     Download     Contact Us    Sales

Veritools, Inc.
459 Hamilton Avenue, Suite 100, Palo Alto, California 94301
(650) 462 - 5590 Main    (650) 462 - 5593 Fax
inquiry@veritools.com

For Web site information please email Webmaster