v2v translators

verilog2vhdl™ and VHDL2verilog™ translators from ASC will help you translate behavioral, synthesizable RTL, or structural designs from one HDL to the other with minimal effort. The output of the translators can be customized for synthesis or simulation. Both tools produce highly readable output by performing smart indentation and preserving comments.

For unsupported constructs, the translators generate informative warnings, which frequently contain references to the workarounds available in the Release Notes. For most cases, the tools continue translation even after encountering an unsupported construct, thus allowing the user to still reap the benefits of automatically translating a major part of input design.

Advantages of using v2v Translators

• Double your market share by supporting both VHDL and Verilog languages. Instead of investing weeks of non-recurring engineering time to develop designs or models in the second language, use v2v translators to do it for you in a fraction of the time.
• Save time in maintenance by keeping designs in one language and translating changes into the other.
• Learn language translation shortcuts and tips as information warnings guide the user. Sometimes a very minor change to the source will make the translation go much smoother. V2v translators exploit commonality between the two languages.
• Decrease language learning time as translators acquaint designers with both Verilog and VHDL. Most engineers have more experience in one of the languages. Using the translation tools builds on what you already know and teaches you as you need to learn. Andy new language appears difficult at the start. The translation tools make learning much easier.
• Make conversions easy and consistent. Single point of control is the key to successful change procedures.

Verilog to VHDL translation

Verilog2vhdl™ translator accepts IEEE 1364-compliant Verilog and produces IEEE 1076-compliant VHDL. Select ’87 or ’93 VHDL style with a command line option.

Key Features

• Functionally equivalent Verilog translation
• Support for behavioral, synthesizable RTL, and structural Verilog
• IEEE 1076-compliant VHDL output for synthesis or simulation
• Selection of translation options through command line switches
• Incremental file-by-file translation
• Syntax and semantic checks
• Comments and hierarchy are preserved
• Functionally accurate translation of Verilog constructs without direct VHDL counterparts
• Supports for many Verilog system tasks and functions, and formatted I/O
• "Black-box" translation of library modules
• Support for testbench-style input

Supported Constructs

Data Types

Verilog2vhdl translator maps the Verilog’s four-value logic using the IEEE 1164 std_logic types. Time, integer, and real types are translated to corresponding VHDL built-in types.

Register and Net Declarations

Two main types of data objects in Verilog are register and net. Nets are translated to signals, and registers to signals or variables, depending on the setting of a command line option.

Parameter Declarations

In Verilog, parameters are used to declare constants. Also, parameters are frequently utilized to parameterize a module, similar to VHDL generics. A command line option allows to user to choose between translating parameters to VHDL constants or generics.

Module Instantiation

Verilog and VHDL are both hierarchical languages and allow instantiating of modules. Methods of instantiation in the two languages are very similar. Thus, Verilog module instantiations are translated to VHDL component instantiations. Parameter overrides and defparam statements are represented through generic maps.

Built-in Gate Instantiations

Part of Verilog’s known flexibility for modeling at low levels of abstraction comes from a library of predefined logic gates. Verilog gate instantiations are translated into VHDL concurrent assignments with the same boolean functionality or instantiations of components from custom packages supplied with the tool.

Always and Initial Blocks

Always and initial blocks are translated to VHDL processes. For an always block, the corresponding process gets the equivalent sensitivity list. Initial blocks that execute only once are translated to processes without the sensitivity list. Edge-sensitive always blocks are translated using VHDL ‘EVENT attribute to represent the signal edge.

Continuous Assignments

Verilog continuous assignments execute every time their right hand side changes. They are translated to equivalent VHDL concurrent signal assignments with inertial delays.

Procedural Assignments

Procedural assignments are used to assign values to registers, and integer, real, or time variables. Blocking assignment, which evaluate immediately, are translated to signal assignments or variable assignments, depending on the command line option setting. Verilog non-blocking assignments are translated to signal assignments only.

Behavioral Modeling

Both Verilog and VHDL have a similar set of constructs for behavioral modeling. Some of them, such as if, case, and while statements, are equivalent in both languages, and are translated respectively. The translation of others is more complex, given the requirements to preserve functional equivalence. Thus, VHDL if statements translate Verilog casex and casez, and VHDL while translates Verilog for, repeat, and forever statements.
Special care is taken to comply with VHDL type checking rules, through measured use of type conversion functions.

User-defined Tasks and Functions

Verilog tasks and functions encapsulate procedural code. They are translated to VHDL procedures and functions, respectively.

System Tasks and Functions

Most Verilog system tasks or functions do not have a direct equivalent in VHDL. verilog2vhdl uses a rich library of packages for VHDL translation of system tasks and functions. The list of supported system tasks and functions includes display, file input-output, and timescale system tasks, and simulation time and type conversion system functions.

Compiler Directives

Verilog compiler directives are translated with the help of a Verilog pre-processor (vpp). verilog2vhdl supports ‘timescale, ‘define, ‘include, and ‘ifdef/ ‘ifndef compiler directives.

          and more.....

This tool is one more member, in a family of extremely powerful tools for Verilog users.  Veritools tools are being used on the world's most demanding Verilog projects including the design of the world's most powerful super computers and many of the largest and demanding ASIC designs currently done in the world.  Veritools products are available on: Sun 4.X, Solaris, HP 700/800, IBM 6000-AIX, Sony News and SGI platforms, in addition to Windows 95 and Windows NT.  One of Veritools products, Undertow, is used world wide by hundreds of companies on 4 continents and in 35 countries.  It has become the standard Verilog, TIMEMILL, POWERMILL, HSpice and Anagram viewing tool in many of the worlds largest electronic companies in the United States, Japan and Europe.

Undertow Suite
Undertow
Interactive_tool
Optimizing_tool
VeriPower
Power_tool
Toggle_tool
Express_VCT
SuperC™
VeriCover
VBIT«
verilog2vhdl™
vhdl2verilog™
Script Pool

Company    Products     News    Assistance     Download     Contact Us    Sales

Veritools, Inc.
459 Hamilton Avenue, Suite 200, Palo Alto, California 94301
(650) 462 - 5590 Main (650) 462 - 5593 Fax
inquiry@veritools.com

For Web site information please email Webmaster