| Verilog To DEF Script
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| # Please feel free to modify this script as you
see fit. # I hereby release it to the public domain (as if anyone # would actually use this). If you make significant # modifications, please email me a copy at # rex@arl.wustl.edu # or send cookies. # # This script converts a verilog netlist (contained in a single # module) into a DEF format file suitable for import into Cadence's # Cell3 layout program. # Outline of the script: #----------------------------- # Print header # DESIGN <name>; # TECHNOLOGY <???>; # UNITS DISTANCE MICRONS 1000; # Count Components, Build Component Array, Build Net Array # Print Components # COMPONENTS <count>; # - <compName> <modelName>; # - <compName> <modelName>; # ... # END COMPONENTS # Count Nets # Print Nets # NETS <count>; # - <netName> (<compName> <portName>) (<compName> <portName>)...; # - <netName> (<compName> <portName>) (<compName> <portName>)...; # ... # Print Trailer # $vlogfilename = $ARGV[0]; ($deffilename = $vlogfilename) =~ s/\.v/.def/; # Find the design name in the file if(!(-r $vlogfilename)) { printf("Can't open file %s\n",$vlogfilename); exit(-1); } open(VLOGFILE,$vlogfilename); open(DEFFILE,">".$deffilename); # Set the line separator to a semicolon $/ = ';'; $done = 0; while(!$done) { $theline = <VLOGFILE>; if($theline =~ /module/) { $done = 1; } } # Grab everything on the line before the first "(" $firsthalf = $theline; $firsthalf =~ s/([^\(]+).*/\1/; # Remove whitespace from beginning of line $firsthalf =~ s/^\s+//; ($module,$designname) = split(/\s+/,$firsthalf); # Grab everything on the line after the first "(" $lasthalf = $theline; $lasthalf =~ s/([^\(]+).*//; printf("Converting verilog file %s into DEF file %s\n",$vlogfilename,$deffilenam e); printf(" module:%s\n",$designname); # Print header printf(DEFFILE "DESIGN %s ;\n",$designname); printf(DEFFILE "TECHNOLOGY ASPEC ;\n"); printf(DEFFILE "UNITS DISTANCE MICRONS 1000 ;\n"); # Grab the pins from the module $done = 0; $pins = 0; while(!$done) { $theline = <VLOGFILE>; if($theline =~ /^\s*wire/) { $done = 1; } else { if(($theline =~ /^\s*input/) || ($theline =~ /^\s*output/) || ($theline =~ /^\s*inout/)) { if($theline =~ /\[/) { # This is a vector, so grab the size $size = $theline; $size =~ s/[^\[]+\[//; $size =~ s/\].*//; ($left,$right) = split(/:/,$size); # Grab the pin name list $pinlist = $theline; $pinlist =~ s/[^\]]+\]//; $pinlist =~ s/;//; $pinlist =~ s/\s//g; if($left < $right) { $min = $left; $max = $right; } else { $min = $right; $max = $left; } @pinarray = split(/,/,$pinlist); for($i=0;$i<=$#pinarray;$i++) { $pins = $pins + ($max - $min + 1); $minarray{$pinarray[$i]} = $min; $maxarray{$pinarray[$i]} = $max; } } else { # This is a single bit list, grab the pin name list # Grab the pin name list $pinlist = $theline; $pinlist =~ s/^\s*[inputout]+//; $pinlist =~ s/;//; $pinlist =~ s/\s//g; # The pinlist should now be a comma-separated list. @pinarray = split(/,/,$pinlist); for($i=0;$i<=$#pinarray;$i++) { $pins = $pins + 1; $minarray{$pinarray[$i]} = -1; $maxarray{$pinarray[$i]} = -1; } } } } } # Print out the pins printf(" pins:%d\n",$pins); printf(DEFFILE "PINS %s ;\n",$pins); foreach $pinname (keys(%minarray)) { if($minarray{$pinname} == -1) { printf(DEFFILE " - %s + NET %s ;\n",$pinname,$pinname); } else { for($i=$minarray{$pinname}; $i<=$maxarray{$pinname}; $i++) { printf(DEFFILE " - %s[%d] + NET %s[%d] ;\n",$pinname,$i,$pinname,$i) ; } } } printf(DEFFILE "END PINS\n"); # Count Components, Build Component Array, Build Net Array $components = 0; $nets = 0; while($theline = <VLOGFILE>) { if($theline =~ /\(/) { # Remove any newlines from the line $theline =~ s/\n//g; # Remove any comments from the line $theline =~ s/\/\*[^\*]+\*\///g; # Copy the line and remove anything after the first "(" $firsthalf = $theline; $firsthalf =~ s/([^\(]+).*/\1/; # Grab the component name and instance name ($slop,$componentname,$instname) = split(/\s+/,$firsthalf); # Bind the instances to components with an associative array if($componentname{$instname} ne "") { printf("ERROR: duplicate instance name: %s\n",$instname); exit(-1); } else { $component{$instname} = $componentname; } # Copy the line and remove anything before the first "(" $lasthalf = $theline; $lasthalf =~ s/[^\(]+//; # Remove any spaces $lasthalf =~ s/\s+//g; # Remove first and last parentheses $lasthalf =~ s/^\(//; $lasthalf =~ s/\);$//; # We should then have a comma separated list # Split the list into parts @pinbinding = split(/,/,$lasthalf); for($i=0;$i<=$#pinbinding;$i++) { ($pinname,$netname) = split(/\(/,$pinbinding[$i]); $pinname =~ s/\.//; $netname =~ s/\)//; if($netbinding{$netname} ne "") { # Append another pin to the list $netbinding{$netname} = $netbinding{$netname}." ( ".$instname." ".$pinname." ) "; } else { # Start a new list $netbinding{$netname} = " - ".$netname." ( ".$instname." ".$pinn ame." ) "; $nets = $nets + 1; } } $components = $components + 1; } } # Print Components printf(" components:%d\n",$components); printf(DEFFILE "COMPONENTS %d ;\n",$components); foreach $instname (keys(%component)) { printf(DEFFILE " - %s %s ;\n",$instname,$component{$instname}); } printf(DEFFILE "END COMPONENTS\n"); printf(" nets:%d\n",$nets); printf(DEFFILE "NETS %d ;\n",$nets); foreach $netname (keys(%netbinding)) { printf(DEFFILE "%s ;\n",$netbinding{$netname}); } printf(DEFFILE "END NETS\n"); # Print out the specialnets (VDD/VSS) section. printf(DEFFILE "SPECIALNETS 2 ;\n"); printf(DEFFILE " - VDD ( * VDD ) + USE POWER ;\n"); printf(DEFFILE " - VSS ( * VSS ) + USE GROUND ;\n"); printf(DEFFILE "END SPECIALNETS\n"); # Print trailer printf(DEFFILE "END DESIGN\n"); |
Other Scripts: Batch Simulation
Products: Undertow Suite
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