VBIT« * : JTAG Test Synthesis for ASIC and IC Designers

Industry's first RT level JTAG Test Synthesis tool now available directly from the original developer ASC  Key Product Features

• Automatic Boundary Scan Test Logic Insertion
• Synthesis to technology independent IEEE 1149.1 macros
• VHDL or Verilog Input •RT Level VHDL or Verilog Output
• Simulation Testbench in Verilog or VHDL for the Boundary ScanCircuitry
• BSDL Output for easy interface to Board Level ATE
• Custom mapping to vendor-specific JTAG cell libraries
• Custom interfaces for internal scan, memory and logic BIST

ASC's VBIT, a high-level JTAG Test Synthesis tool, frees engineers from the tedium of learning the details of IEEE 1149.1 standard and manually inserting boundary scan test logic into their ASIC, IC or MCM designs. VBIT automates the entire process.

Promotes Design Re-use
ASC was the first to introduce a JTAG Test Synthesis tool which accepts both Verilog and VHDL and automatically generates technology-independent boundary scan implementation at RT level thus promoting design re-use. Other tools lacking RT level boundary scan test insertion are used too late in the design cycle to be truly technology
independent.

Furthermore, by implementing boundary scan before logic synthesis, the designers can synthesize functional core logic and test logic concurrently and avoid timing and area violations in the entire chip. This saves costly design iterations.

Why ASC's VBIT Boundary Scan?
JTAG IEEE 1149.1 continues to be a preferred method for reducing component, board, and system test costs. Increasing number of designers are implementing boundary scan test logic into their chip designs. Engineers planning to incorporate boundary scan in their designs for the first time can avoid the tedium of learning the implementation details of the IEEE 1149.1 standard by integrating ASC's VBIT automatic boundary scan test
synthesis tool into their design flow.

After a chip designer has described the core logic in either VHDL or Verilog, VBIT takes that input, synthesizes the boundary scan, and outputs a new VHDL or Verilog file with test logic inserted, interconnected and wired to the core logic. The output is compliant with the IEEE 1149.1 standard. The tool also extends the JTAG standard by allowing the test access port (TAP) controller to be connected to internal test structures,
such as scan, thus making the TAP controller the test manager for full-chip test.

VBIT also generates a testbench which allows automatic verification of the boundary scan circuitry at RT level. This test bench is needed for lower level tests as well. For board testing, VBIT automatically writes out a BSDL description of the synthesized boundary scan logic.

The entire process is automated and is IEEE 1149.1 compliant.

Engineers who have struggled with manually inserting or using partially automatic tools to insert IEEE 1149.1 compliant boundary scan can cut that portion of the design time from weeks or months to a few days or hours. They will also appreciate the automatic generation of the BSDL file describing the synthesized boundary scan logic, a feature absent from many of the available tools.

Why at RT Level?
Tools that work at the structural level insert boundary scan after logic synthesis and, sometimes, after the completion of logic and timing verification. Boundary scan insertion at this stage can violate area and timing constraints, and require additional verification steps that may add costly design iterations.

VBIT allows the designer to incorporate test logic in the earliest phase of the top-down design process. With a complete specification of test logic and core design, the synthesis and optimization process gives the designer a true picture of the chip performance.

By implementing boundary scan at RT level, the engineer can also maintain the technology independence of the design. Furthermore, the boundary scan test logic portion can be re-targeted to the ASIC vendor's pre-defined JTAG library which is optimized for area and speed. This technology- specific high-level mapping, which is effectively implemented only at RT level yields better area and speed than a generic library.

This tool is one more member, in a family of extremely powerful tools for Verilog users.  Veritools tools are being used on the world's most demanding Verilog projects including the design of the world's most powerful super computers and many of the largest and demanding ASIC designs currently done in the world.  Veritools products are available on: Sun 4.X, Solaris, HP 700/800, IBM 6000-AIX, Sony News and SGI platforms, in addition to Windows 95 and Windows NT.  One of Veritools products, Undertow, is used world wide by hundreds of companies on 4 continents and in 35 countries.  It has become the standard Verilog, TIMEMILL, POWERMILL, HSpice and Anagram viewing tool in many of the worlds largest electronic companies in the United States, Japan and Europe.

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