New State diagram view of your Verilog Source Code State Diagrams are automatically generated from the users source code. Users can display a single state diagram or multiple statediagrams. The State Diagram View provides the user with several powerful new analysis features including, State Stepping, both forward and backward ,State Path Analysis, State Coverage, and State Coincidence Analysis.
New RTL and Gate Schematics
The Schematic files are now automatically generated directly from the users source code files. These schematics can be gate level or RTL level schematics. RTL level schematics allow the user to see all sections of their RTL design graphically and to quickly find drivers and loads from the schematic window.
Undertow IX Suite now brings the ease of use of
Undertow to the source code debugging environment. A new user interface allows the user to
easily and quickly move between the different views effortlessly
. Users can go from an edge of a signal on Undertow, to the exact
line of source code on the Source Code Window, and then trace back the drivers for the
signals on this line of code to their original source, even through different modules.
Users can drop and drag State Machine Blocks from the RTL Schematic Window onto the State Diagram Window to see the exact state diagram, and then see what lines of source code correspond to this state diagram in the Source Code Window. Users can view and step any state machine, or any number of state machine at the same time to see the interaction between these state machines. Users can even see state machine interaction within the same time point.
Users can select a single state on any diagram and fully explore what other state machine are doing during this state.
Undertow IX Suite also now includes a complete state coverage tool as a standard feature of this tool set so that users can see exactly which states have been tested and which states have not been tested.
Undertow IX Suite is a "NO COST" upgrade to Undertow VIII Suite users.
Users of Undertow only, can upgrade to Undertow IX Suite, which includes the Interactive_tool for only a very small incremental cost.
The EDA industry's only UNIVERSAL™ and fully integrated debugging environment. Undertow Suite is a complete suite of tools to enable design engineers to debug from a common interface.
Undertow Suite Tools:
Undertow: With Graphical
Schematic and standard scripting tool
Interactive_tool: Now with
Source Code Annotation, traceback, and HDLLint
Optimizing_tool: Allows vcd
file compression up to 100X, and can speed up your expensive Verilog simulator by up to
3X.
Veritools is known in the industry as the EDA vendor that helps its customers solve their
problems quickly, and is committed to deliver the EDA industry's highest, most compatible
performing debugger tools. An integrated suite that will significantly increase the
performance of your design verification tools.
- Speed up your simulator by up to 2x
- Undertow Suite will significantly shorten your design cycle
- Easy tool integration Plug-and-Play
- Customer Support and Training
Working together in a tightly integrated environment, these tools can be used to quickly display and analyze your simulation results allowing you to rapidly identify problems in your source code or structural code.
- The wave form analyzer ( Undertow ) because of its unbeatable performance, it has become the standard waveform viewer for the worlds most demanding design projects.
- The source code debugging environment provides source code viewing, stopping , and now trace back for quick analyzers to source of most design problems. A unique source code trace capability is also provided to see exact execution of source code.
- Both debugging and comprehensive schematic generation are provided for both RTL and structural Verilog design.
- All displays are not only synchronized ( waveform, source code, schematic ) but provide a rapid and totally integrated environment, edges of waveforms can be connected to the exact line of source code, source code variables can be added or found on the waveform display instantly, schematics can be shown for any signal in the waveform display.
- A powerful compare feature is provided which provides for example RTL to gate simulations comparisons, which can then be linked to schematics or source code to identify differences.
- Interactive Source Code debugging with Back Annotation, Traceback, and Finite State Machine enabled
Veritools world wide dominating product line is a family of extremely powerful tools for Verilog and VHDL users. Veritools tools are being used on the world's most demanding Verilog projects including the design of the world's most powerful super computers and many of the largest and most demanding ASIC designs currently done in the world. Veritools products are available on Sun Sparc, HP 700/800, SGI, IBM RS 6000 workstations, LINUX x86 PC, Windows 95 and Windows NT. One of Veritools products, Undertow, is used world wide by hundreds of companies on 4 continents and in 35 countries. It has become the standard Verilog, TIMEMILL, POWERMILL, HSpice and Anagram viewing tool in many of the worlds largest electronic companies in the United States, Japan and Europe.
Undertow Suite
Undertow
Interactive_tool
Optimizing_tool
VeriPower
Power_tool
Toggle_tool
SuperC™
Express_VCT
VeriCover
VBIT«
verilog2vhdl™
vhdl2verilog™
Script Pool
The Industry's most accurate Finite State Machine Analyzer
Complete Verification Suite
The Industry's only "UNIVERSAL TOOL™"
Gate and RTL Level Graphical Schematic Tool
Reduce expensive design time with Undertow Suite IX
Fastest Debugging Suite Viewer on the EDA Market!
Intuitive User Friendly Setup and Operation