PLI routine that performs a toggle coverage analysis of the Verilog design

Toggle_tool is a PLI based routine that determines the toggle coverage of a design during a Verilog simulation. It is useful for Verilog designers who are writing test vectors for their design. It is a more complete version of Undertow's Toggle Analyzer.  However, since it does not require a VCD file it can test much larger designs over much longer simulation times.

Full toggle coverage during Verilog simulation: the Toggle_tool PLI routine is enabled at simulation time and produces a toggle report of nodes that have not switched.
Time window for toggle analysis: the Toggle_tool allows the user to specify a timing window, either in absolute time values or relative to a signal's edge or value.
Selective test procedure: The user can specify the signals to test or the signals to ignore.
Database capability: Toggle_tool features a database that lets the user store the results of previous simulations, and to accumulate information on toggle coverage.
Statistical information on multiple simulation runs: Toggle_tool provides statistical information on the toggle analysis and can merge multiple runs.
Toggle report: Toggle information can be output as a toggle report or output as a list that can be used by Undertow V using Toggle Analyzer to further study the toggle analysis.
Negligible overhead during simulation: determining toggle coverage during Verilog simulations adds very little overhead to the simulation load.

Description:

Toggle_tool is a PLI routine that determines toggle coverage of a Verilog1 design during simulation. It is targeted at users who are writing test vectors for their design. It will not only determine which nodes have not toggled over a specified period of time but will also provide statistical measures of toggle coverage for a design. The toggle output results can be merged across different simulation runs.

The PLI routine can be run with the following options:

- time windows for toggle analysis which can consist of:
- absolute time values
- time values relative to a signal's edge
- time values relative to a signal's value
- list of signals to ignore/test
- output to screen/file/printer

The output report contains the following information:

- test case options indicating which signals the toggle analysis was performed on
- list of signals that do not toggle
- statistical information on the toggle coverage of the Verilog design

Here is a sample output from Toggle_tool:

Toggle analysis of file: test_case_3
Time window: 30000 to 120000
List of signals to ignore: signal_to_ignore.3
Signals that did not toggle :
TOP/trsmt/pn0
TOP/trsmt/pn3
TOP/trsmt/nFrameHeader
TOP/store/nBufferOutputReady
TOP/store/nTxState
TOP/store/nWrBuffer
TOP/Rx1/chksum[31:0]
Toggle coverage: 85.9%
Variation versus last simulation: 7.4%
Average improvement of the toggle coverage: 6.6%

This tool is useful during the test vector development. It is an important first step before proceeding with fault grading. The database feature allows the user to accumulate toggle information over many simulation runs, with each run adding incrementally to the toggle statistics.

The Toggle_tool adds very little additional computational overhead to the Verilog simulation. This tool is designed with code that meets the OVI standard, and hence will link with any Verilog simulator that also compiles with this standard. It has been tested with Verilog-XL and VCS from Chronological.

and more.....

This tool is one more member, in a family of extremely powerful tools for Verilog users.  Veritools tools are being used on the world's most demanding Verilog projects including the design of the world's most powerful super computers and many of the largest and demanding ASIC designs currently done in the world.  Veritools products are available on: Sun 4.X, Solaris, HP 700/800, IBM 6000-AIX, Sony News and SGI platforms, in addition to Windows 95 and Windows NT.  One of Veritools products, Undertow, is used world wide by hundreds of companies on 4 continents and in 35 countries.  It has become the standard Verilog, TIMEMILL, POWERMILL, HSpice and Anagram viewing tool in many of the worlds largest electronic companies in the United States, Japan and Europe.

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