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The fastest Verilog coverage tool in the world


Express VCT, is a powerful source code test coverage tool that allows the designers of Verilog behavioral code to see what coverage their test are providing for their code.
This tool includes:

  • Speed: Express VCT is designed to give the user the fastest possible coverage results
  • A test generator: Express VCT reads in the Verilog source code and generates a test suite that can be used to monitor the simulation as it runs.
  • Verilog source code covered: Tests are generated for the conditional logic found in continuous assignment statements and always @ blocks.
  • Types of tests: the two types of tests that are generated are, branch coverage, and multi-conditional.
  • Continuous assignments: multi-conditional coverage tests are generated for continuous assignment statements. The right hand side of the assignment is converted to a sum-of-products with each term in the sum-of-products generating a test for that term that must evaluate to TRUE, while all other terms evaluate to FALSE.
  • always @ Block: tests are generated for both if and case statements
  • if statements: generate both a branch coverage test and a multi-conditional. The branch tests that the condition portion of the statement is evaluated at least once to both a TRUE and a FALSE. The multi-conditional test converts the condition portion of the statement into a sum-of-products with a test for each term that checks that the term is evaluated to a TRUE while all other terms evaluate to a FALSE
  • Case statement: generate a test for each branch of the case statement to check if the branch has been evaluated
  • Report generation: is provided with text output, or output result can be viewed graphically.


DESCRIPTION

Express VCT reads in Verilog source descriptions and generate a database of coverage tests which will monitor the Verilog simulation as it is run, using PLI routines .

The tests are generated for continuous assignments and always @ blocks. Express VCT will generate two different types of coverage tests. The first type of coverage test is branch coverage. These types of tests determine which blocks defined by if and case statements have been executed. For an if statement, a test is generated which will check that the condition portion is
evaluated at least once to both a TRUE and a FALSE. For a case statement, a test is generated for each branch of the case statement to check if the branch has been evaluated. The second type of coverage test is a multi-conditional test. This tests what part of a conditional statement's truth table has been covered. The condition portion of a conditional statement is converted into a
sum-of-products. A test is then generated for each term in the sum-of-products. The test will check that the term is evaluated to a TRUE while all other terms evaluate to a FALSE.

Continuous Assignments statements will generate only multi-conditional coverage tests. The right hand side of the assignment will be converted to a sum-of-products. Each term in the sum-of-products will generate a test for that term to be evaluated to TRUE with all other terms to be evaluated to FALSE. These tests will occur at the end of a simulation time unit in which a variable in the sum-of-products switches. Therefore, zero delay switches will not be counted as a hit for the test. If a clock is specified for the test, the evaluation of the terms will occur at the end of the simulation time unit in which the specified clock edge occurs.

Within always @ Blocks

if statements generate both a branch coverage test and a multi-conditional test. The branch coverage test generated will check that the condition portion of the statement is evaluated at least once to both a TRUE and a FALSE. For the multi-conditional test the condition portion of the statement is converted into a sum-of-products. A test for each term will be generated. The test will
check that the term is evaluated to a TRUE while all other terms evaluate to a FALSE. This check will occur only during the execution of the always @ block which contains the if statement. If a statement contains an if statement as one of it's clauses, the embedded if statement will also generate it's own tests.

case statements will generate a branch coverage test for each branch of the case statement. Express VCT comes with a complete report generator, or the user can graphically view highlighted source code files which show lines of code that have not been completely covered by the current vector set.

Express VCT uses PLI routines to communicate with the Verilog simulator. Any Verilog simulator that supports the OVI standard set of PLI routines will work with Express VCT.

          and more.....

This tool is one more member, in a family of extremely powerful tools for Verilog users.  Veritools tools are being used on the world's most demanding Verilog projects including the design of the world's most powerful super computers and many of the largest and demanding ASIC designs currently done in the world.  Veritools products are available on: Sun 4.X, Solaris, HP 700/800, IBM 6000-AIX, Sony News and SGI platforms, in addition to Windows 95 and Windows NT.  One of Veritools products, Undertow, is used world wide by hundreds of companies on 4 continents and in 35 countries.  It has become the standard Verilog, TIMEMILL, POWERMILL, HSpice and Anagram viewing tool in many of the worlds largest electronic companies in the United States, Japan and Europe.

  

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